As the physical dimensions of very large scale integrated circuits (VLSI) continue to shrink, it has become increasing difficultly to manufacture such integrated circuits reliably. In current complex chip designs, fully functional interconnections between wires and pins associated with various components such as, for example, diodes, capacitors, resistors transistors, etc. are essential in order to ensure reliable operation of a chip.
As VLSI technology migrates towards the 90 nanometer range and below, the sensitivity of a VLSI design to random defects such as opens and/or shorts, increases as the number of components or features being placed on a chip increases and spacing between components decreases. Furthermore, as current manufacturing techniques evolve to keep pace with the shrinking chip sizes, these techniques have become even more sensitive to chip yield rate, which is generally defined as a percentage of fully functional dies relative to a total number of dies on a wafer. In addition, opens and shorts of interconnections can have a great impact on the yield rate.
Current approaches to improve yield rate have focused primarily on mitigating the effects due to open defects or faults. Moreover, some of the techniques currently being implemented to mitigate the effects of open faults, can inadvertently increase the occurrence of short faults, and can thereby further decrease chip yield.
Therefore, there is a need for more efficient methods and systems that can consider the effects of both open and short defects to improve chip yield rate.